1. Field of the Invention
The present invention relates to a data processor. The present invention more particularly relates to a technique of checking indefined addressing which is prescribed for each instruction in a microprocessor decoding and executing a train of instructions including a plurality of sets of an instruction code field (hereinafter referred to as an operation code) and a corresponding addressing field.
2. Description of the Related Art
As examples of a train of instructions having a plurality of operation codes and a corresponding plurality of addressing fields, a train of instructions of variable length are known which consist of instruction formats, e.g., as shown in FIG. 9. In the illustration, an operand field OPD corresponds to the addressing field, and an instruction code field OP corresponds to the operation code. The operation code defines the kind of an instruction. By decoding the operation code, the addressing field is checked to see whether it is undefined or defined. Usually, an addressing field is arranged after an operation code. Accordingly, for example, where there is only one operand as shown in FIG. 9a, an operation code OP is first decoded and a corresponding addressing field OPD is then checked to see whether it is undefined or defined. Where the addressing field is defined, the instruction is executed, and where the addressing field is undefined, the execution of the instruction is stopped.
In some trains of instructions, however, there is a case that an addressing field to be checked by an operation code is arranged before the operation code concerned. For example, in decoding a train of instructions including two operands as shown in FIG. 9b, when a second operation code OP is decoded, an addressing field OPD of a preceding operand (a first operand) can be checked to see whether it is undefined or defined. In this case, where the first addressing field OPD is defined, an instruction for the first operand can be executed when the second operation code OP is decoded. Where the first addressing field OPD is undefined, however, the execution of the instruction for the first operand must be stopped by means of a proper processing.
To cope with this matter, a special execution cycle may be set to check an operand for its undefined or defined addressing. Where a microprocessor executes a pipeline processing, however, there is a possibility in that the checking cannot be completed within the prescribed cycle. Namely, a result of the checking may be provided in the next cycle or later. This may delay execution of instructions and thus lower an instruction execution performance of the microprocessor.